1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus for testing, for example, various semiconductor devices such as semiconductor memories or logic ICs with memories mounted.
2. Description of the Related Art
FIG. 4 shows an outline of a conventional semiconductor device testing apparatus. FIG. 4 shows a configuration depicted by paying an attention only to signal paths in the testing apparatus. A pattern generating part 11 outputs signals or data such as an X address signal XAD, a Y address signal YAD, first and second device control signals MUS1 and MUS2, a test pattern data TP containing an expected value data EX, and the like which are to be applied to a semiconductor device under test 10.
A programmable data selecting part 12 classifies those signals or data in accordance with specifications of each pin of the semiconductor device under test 10, and allocates those signals to corresponding channels in the semiconductor device testing apparatus.
An input signal cycle delaying part 13 gives each signal a delay that agrees with the specifications of each input pin of the semiconductor device under test 10, and further adjusts its voltage level and pulse width in accordance with the specification conditions to supply the delayed and adjusted signal to the semiconductor device under test 10 as an input signal SIN.
On the other hand, an expected value data EX allocated to an expected value data channel by the programmable data selecting part 12 is supplied to a logical comparison part 15 through an expected value data transmission path 17 as an expected value data EX after a delay that agrees with output specifications of the semiconductor device under test 10 is given thereto by an expected value data cycle delaying part 14.
The logical comparison part 15 compares a response output signal SOUT outputted from the semiconductor device under test 10 with an expected value data EX given through the expected value data transmission path 17. When a discordance occurs in the comparison, for example, a logical xe2x80x9c1xe2x80x9d representing a failure is set in a bit position where the discordance occurred, and failure data FL 10, FL11, FL12, - - - each being able to specify a failure cell position based on this failure bit position are outputted from the logical comparison part 15.
Each of the failure data FL10, FL11, FL12, - - - is inputted to a data failure memory 16, and the data failure memory 16 is switched to writing mode by the input of each of the failure data FL10, FL11, FL12, - - - . An X address signal XAD, a Y address signal YAD, first and second device control signals MUS1 and MUS2, and a test pattern data TP containing an expected value data EX outputted from the pattern generating part 11 at a time point when each of the failure data FL10, FL11, FL12, - - - is generated are acquired and stored in the data failure memory 16 via a data transmission path 18 without any time delay.
Here, types of failure memories to be mounted in a semiconductor device testing apparatus will briefly be explained below. There are two types of failure memories each being to be mounted in a semiconductor device testing apparatus. One of the two types is an address failure memory that has the same address area as that of the semiconductor device under test, and the other is a data failure memory that stores therein failure data, address data, and test pattern data.
An address failure memory requires a large memory capacity since it has the same address area as that of the semiconductor device under test. That is, memory capacity is becoming larger and larger every year, and if the number of semiconductor devices tested at the same time becomes larger from, for example, current 32 to 64 or 128 etc., there is a drawback, in an address failure memory, that the same number of failure memories as the number of semiconductor devices under test must be mounted on a testing apparatus, and therefore the cost of the mounted failure memories becomes extremely high.
On the contrary, if the number of failure occurrences is small, failure memory capacity of a data failure memory may be small. Therefore, in order to provide a less expensive semiconductor device testing apparatus, a semiconductor device testing apparatus of a type on which a data failure memory 16 is mounted is advantageous.
From such a background, a semiconductor device testing apparatus on which a data failure memory is mounted is used in many cases. However, data to be stored in the data failure memory 16 are an X address signal XAD, an Y address signal YAD, a test pattern data TP, and the like outputted from the pattern generating part 11 at a time when a failure is detected. Therefore, since an address where a failure occurred, a test cycle when a failure occurred, or the like are to be estimated from these data, there is a drawback that it takes a longer time and more workload for a failure analysis.
This situation will be explained below using FIG. 5. The indication A in FIG. 5 shows an X address signal XAD, an Y address signal YAD, a test pattern data TP, and first and second device control signals MUS1 and MUS2 outputted from the pattern generating part 11.
An X address signal XAD outputted from the pattern generating part 11 is supplied to the semiconductor device under test 10 as a row address signal ROW1, and a Y address signal YAD is supplied to the semiconductor device under test 10 as one of column address signals COL10, COL11, COL12, COL13, - - - .
In addition, in this example, there is shown a case where a read command READ is applied, as the second device control signal MUS2, to each of four addresses (ROW1, COL10; ROW1, COL11; ROW1, COL12; ROW1, COL13) to be accessed by the row address ROW1 and the column addresses COL10-COL13. Further, as the first device control signal MUS1, is applied a control signal ACT for directing the semiconductor device under test l0 to acquire a row address. In addition, EX10, EX11, EX12, EX13, - - - are expected value data that are logically compared respectively with response output signals RD10, RD11, RD12, RD13, - - - (refer to FIG. 5B) outputted from the semiconductor device under test 10 in accordance with the read command READ.
Those signals outputted from the pattern generating part 11 are delayed, if each of their output timings (t=0) is referred to as an initial timing of each signal, by the input signal cycle delaying part 13 and the expected value data cycle delaying part 14 shown in FIG. 4 to the state shown in B and C of FIG. 5, and are inputted to the semiconductor device under test 10 and the logical comparison part 15 through their corresponding transmission paths.
That is, each of the address signals COL10, COL11, COL12, COL13, - - - to be applied to the semiconductor device under test 10 is delayed by two test cycles (t=2xcfx84) from its initial timing (t=0) at which the corresponding row address signal ROW1 is applied, and then is supplied to the semiconductor device under test 10. This time delay is determined by a characteristic of the semiconductor device under test 10. Moreover, there is shown a case in which each of the read command signals READ is also delayed by two test cycles, and is applied to the semiconductor device under test 10.
In addition, in this example, there is shown a case in which each of the response output signals RD10, RD11, RD12, RD13, - - - of the semiconductor device under test 10 is delayed by three test cycles from a timing at which the corresponding read command signal READ is applied, and is outputted (refer to B of FIG. 5).
Therefore, each of the response output signals RD10, RD11, RD12, RD13, - - - is outputted at a timing delayed by five test cycles (t=5xcfx84) from its output initial timing of the pattern generating part 11.
For this reason, each of the expected value data EX10, EX11, EX12, EX13, - - - is applied to the logical comparison part 15, as shown in C of FIG. 5, at a timing delayed by the expected value data cycle delaying part 14 by five test cycles from its initial timing, and is logically compared with corresponding one of the read data RD10, RD11, RD12, RD13, - - - . FL10, FL11, FL12, FL13, - - - shown in C of FIG. 5 represent failure data that are created due to the discordances in the respective comparisons.
D of FIG. 5 shows timings of the respective data being inputted to the data failure memory 16. According to the configuration of the semiconductor device testing apparatus shown in FIG. 4, an X address signal XAD, a Y address signal YAD, a test pattern data TP, and first and second device control signals MUS1 and MUS2 are inputted to the data failure memory 16 without being delayed. Therefore, at the timing when each of the failure data FL10, FL11, FL12, FL13, - - - is generated, a data generated from the pattern generating part 11 after five test cycles from each corresponding initial timing is acquired and stored in the data failure memory 16.
As apparent from D of FIG. 5, the cycle of the data generated from the pattern generating part 11 does not accord with the cycle of the failure data at the data failure memory.
Therefore, in the case of performing a conventional failure analysis, a series of pattern sequences that is stored in the pattern generating part 11 and is outputted therefrom in synchronism with test cycles must be referred, and a data leading by five test cycles from the failure data being analyzed must be searched in the data stored in the data failure memory 16 to estimate the address where the failure occurred and the pattern data by which the failure was detected. Therefore, in this case, there is a drawback that much more workload and longer time are spent.
In addition, there are two methods of failure analysis, i.e., (1) to perform a failure analysis by specifying an address where a failure occurred, a data read out from the address where the failure occurred, and an expected value used for the comparison, or (2) to perform a failure cause analysis by specifying addresses and device control signals which have been actually applied to the semiconductor device under test until a time when a failure occurs and expected values which have been applied to the logical comparison part until the time when the failure occurs. Since the reference position in the pattern series (a test cycle position to be referred) is different depending on which method of the (1) and (2) is used for the failure analysis, the work is very cumbersome.
It is an object of the present invention to provide a semiconductor device testing apparatus in which a data stored in the data failure memory can be used as the right data to be obtained even in either case of the failure analysis methods.
In order to achieve this object, the semiconductor device testing apparatus according to the present invention includes a variable delay part that gives a delay of arbitrary cycles to a data from the pattern generator to be stored in the data failure memory to thereby supply the delayed data to the data failure memory.
As a first configuration of the present invention, in a semiconductor device testing apparatus of a type having a configuration that an address signal, a device control signal and a test pattern data outputted from a pattern generating part are applied to a semiconductor device under test, a response output signal from the semiconductor device under test is compared by a logical comparison part with an expected value data outputted from the pattern generating part, and at a time when a discordance occurs in the comparison result, an address signal, a test pattern data containing an expected value data, and device control signals outputted from the pattern generating part at that time are stored in a data failure memory together with a failure data representing a failure cell position, there is proposed a semiconductor device testing apparatus wherein a variable delay part is provided on a data transmission path connecting the pattern generating part to the data failure memory, based on a delay time set in the variable delay part, an arbitrary delay is given to each of the address signal, the test pattern data containing the expected value data and the device control signals outputted from the pattern generating part at the time the discordance occurs, and those data thus delayed can be stored in the data failure memory.
As a second configuration of the present invention, in the semiconductor device testing apparatus having the first configuration, there is proposed a semiconductor device testing apparatus having a configuration that based on the delay time set in the variable delay part, an address data representing a failure memory cell of the semiconductor device under test where the failure occurred, a test pattern data applied to the address where the failure occurred, and an expected value data to be compared with a response output data of the address where the failure occurred are stored in the same address of the data failure memory for storing a failure data.
As a third configuration of the present invention, in the semiconductor device testing apparatus having the first configuration, there is proposed a semiconductor device testing apparatus having a configuration that based on the delay time set in the variable delay part, address signals having been applied to the semiconductor device under test until a time when a failure occurs, and expected value data having been applied to the logical comparison part until the time when the failure occurs are stored in the data failure memory.
According to the semiconductor device testing apparatus of the present invention, a timing of a data to be stored in the data failure memory at a time of a failure occurrence can arbitrarily be selected by appropriately setting a delay time of the variable delay part.
As a result, when a test pattern actually applied to an address of a semiconductor device under test where a failure occurred and the corresponding response output are read out, the response output data can be stored in the data failure memory in correlation to an expected value data which is to be compared. In addition, at a time point when a failure occurs, an address signal currently being applied to the semiconductor device under test and an expected value data being applied to the logical comparison part can be stored in the same address of the data failure memory.
Therefore, at a time of failure analysis, a test pattern applied to an address where a failure occurred or the state of an address signal and a device control signal applied to the semiconductor device under test at a failure occurrence time can immediately be read out from the data failure memory. Consequently, there is obtained an advantage that the workload required for a failure analysis can greatly be reduced.